1. Field of the Invention
The present invention relates to a data processing circuit for multiplying, by 2.sup.a, input data supplied in a time-division multiplexed manner over a plurality of lines, for example.
2. Description of the Prior Art
Digital data processing circuits make a wide use of multipliers. To reduce the size of a digital data processing circuit, it is therefore required to reduce the size of the multipliers used because they are larger in circuit scale than adders.
FIG. 1 of the accompanying drawings shows a conventional multiplier. The multiplier shown in FIG. 1 comprises a plurality of connected adder circuits 1A, 1B, . . . each composed of a plurality of full adders.
The conventional multiplier is however large in overall circuit scale as it is simply made of plural connected adder circuits each comprising a plurality of full adders.
According to one proposal, a multiplier may comprise a combination of a processing circuit for multiplying each item of input data by 2.sup.a (a= . . . , -2, -1, 0, 1, 2, . . . ) and adder circuits. The input data may be transmitted in a time-division multiplexed manner over a plurality of lines to the multiplier.
Some systems for transmitting input data in a time-division multiplexed fashion will be described below with reference to FIGS. 2A, 2B, and 2C.
In the system shown in FIG. 2A, data rows A, B, C, . . . each having a word length of 3 bits are successively transmitted over a single signal line. More specifically, if it is assumed that the 3-bit data rows A, B, C, . . . are indicated by A=(A2, A1, A0), B=(B2, B1, B0), C=(C2, C1, C0), . . . , respectively, then the data are successively transmitted in the sequence of A0, A1, A2, B0, B1, B2, C0, . . . one bit in a cycle over the signal line.
In the system shown in FIG. 2B, data rows A, B, C, . . . each having a word length of 6 bits are transmitted as data of high-order 3 bits and low-order 3 bits over two signal lines. More specifically, if it is assumed that the 6-bit data rows A, B, C, . . . are indicated by A=(A5, A4, A3, A2, A1, A0), B=(B5, B4, B3, B2, B1, B0), C=(C5, C4, C3, C2, C1, C0), . . . , respectively, then the data are successively transmitted in the sequence of A0, A1, A2, B0, B1, B2, C0, . . . one bit in a cycle over the first signal line, and in the sequence of A3, A4, A5, B3, B4, B5, C3, . . . one bit in a cycle over the second signal line with a delay of 3 cycles with respect to the first signal line.
In the system shown in FIG. 2C, data rows A, B, C, . . . each having a word length of 9 bits are transmitted as data of high-order 3 bits, middle-order 3 bits, and low-order 3 bits over three signal lines. More specifically, if it is assumed that the 9-bit data A are indicated by A=(A8, . . . , A1, A0), then the low-order bits (A0, A1, A2) are transmitted over the first signal line, the middle-order bits (A3, A4, A5) are transmitted over the second signal line with a delay of 3 cycles, and the high-order bits (A6, A7, A8) are transmitted over the third signal line with a further delay of 3 cycles. If it is assumed that the 9-bit data B are indicated by B=(B8, . . . , B1, B0), then the bits (Bj, Bj+1, Bj+2) of the data B are transmitted, following the bits (Aj, Aj+1, Aj+2) of the data A, over the signal lines. The bits of the data C are thereafter transmitted following the data B.
According to a generalization of the data transmission systems shown in FIGS. 2A, 2B, and 2C, data rows A, B, C, . . . each having a word length of n (n is a multiple of 3) can be transmitted in a time-division multiplexed fashion over n/3 signal lines. The data structure of the data rows is expressed by the following equations (1): EQU A=(An-1, An-2, . . . , A1, A0), EQU B=(Bn-1, Bn-2, . . . , B1, B0), EQU C=(Cn-1, Cn-2, . . . , C1, C0) (1)
where An-1, Bn-1, Cn-1 are MSBs and A0, B0, C0 are LSBs.
The data rows according to the equations (1) can also be transmitted in a time-division multiplexed manner over 2.times.n/6 signal lines, as shown in FIGS. 3A, 3B, and 3C. FIG. 3A shows a data transmission system in which data rows A, B, C, . . . each having a word length of 6 bits are transmitted over two signal lines. FIG. 3B shows a data transmission system in which data rows A, B, C, . . . each having a word length of 12 bits are transmitted over four signal lines. FIG. 3C shows a data transmission system in which data rows A, B, C, . . . each having a word length of 18 bits are transmitted over six signal lines. Furthermore, data rows A, B, C, . . . each having a word length of n (n is a multiple of 4) can be transmitted in a time-division multiplexed fashion over n/4 signal lines.